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M95040 M95020, M95010
4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
FEATURES SUMMARY s Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes)
s
Figure 1. Packages
Single Supply Voltage: - 4.5V to 5.5V for M950x0 - 2.5V to 5.5V for M950x0-W - 1.8V to 3.6V for M950x0-S
s s s s s s s s
5 MHz Clock Rate (maximum) Status Register BYTE and PAGE WRITE (up to 16 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 1,000,000 Erase/Write Cycles More than 40 Year Data Retention
8 1
PDIP8 (BN)
8 1
SO8 (MN) 150 mil width
TSSOP8 (DW) 169 mil width
July 2003
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SUMMARY DESCRIPTION The M95040 is a 4 Kbit (512 x 8) electrically erasable programmable memory (EEPROM), accessed by a high speed SPI-compatible bus. The other members of the family (M95020, M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 2. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD). WRITE instructions are disabled by Write Protect (W). Figure 2. Logic Diagram
Note: 1. See page 28 (onwards) for package dimensions, and how to identify pin-1.
Figure 3. DIP, SO and TSSOP Connections
M95xxx S Q W VSS 1 2 3 4 8 7 6 5
AI01790D
VCC HOLD C D
VCC
Table 1. Signal Names
D C S W HOLD M95xxx Q
C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground
S
W HOLD VCC
VSS
AI01789C
VSS
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SIGNAL DESCRIPTION VCC must be held within the specified range: VCC(min) to VCC(max). All of the input and output signals can be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Tables 12 to 16). These signals are described next. Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data bytes are shifted out on the falling edge of the Serial Clock (C). Serial Data Input (D) This input signal is used to transfer data serially into the device. Instructions, addresses, and input data bytes are shifted in on the rising edge of the Serial Clock (C). Serial Clock (C) This input signal provides the timing for the serial interface.
Chip Select (S) When this input signal is High, the device is deselected, and the Serial Data Output (Q) is high impedance. Hold (HOLD) This input signal is used to pause temporarily any serial communications with the device, without losing bits that have already been passed on the serial bus. Write Protect (W) This input signal is used to control whether the memory is write protected. When W is held Low, writes to the memory are disabled, but other operations remain enabled. No action on this signal, or on the Write Enable Latch (WEL) bit, can interrupt a Write cycle that has already started.
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CONNECTING TO THE SPI BUS These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 4 shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance.
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD Bus Master (ST6, ST7, ST9, ST10, Others) SPI Memory Device CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI Memory Device SPI Memory Device CQD CQD
AI03746D
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: - CPOL=0, CPHA=0 - CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data: - C remains at 0 for (CPOL=0, CPHA=0) - C remains at 1 for (CPOL=1, CPHA=1)
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Figure 5. SPI Modes Supported
CPOL
CPHA C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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OPERATING FEATURES Power-up When the power supply is turned on, V CC rises from VSS to VCC. During this time, the Chip Select (S) must be allowed to follow the V CC voltage. It must not be allowed to float, but should be connected to VCC via a suitable pull-up resistor. As a built in safety feature, Chip Select (S) is edge sensitive as well as level sensitive. After Powerup, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been High, prior to going Low to start the first operation. Power mode, and the device consumption drops to ICC1. Hold Condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as Serial Clock (C) already being Low (as shown in Figure 6). The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being Low.
Power-down At Power-down, the device must be deselected. Chip Select (S) should be allowed to follow the voltage applied on V CC. Active Power and Stand-by Power Modes When Chip Select (S) is Low, the device is enabled, and in the Active Power mode. The device consumes ICC, as specified in Tables 12 to 16. When Chip Select (S) is High, the device is disabled. If an Erase/Write cycle is not currently in progress, the device then goes in to the Stand-by Figure 6. Hold Condition Activation
C
HOLD
Hold Condition
Hold Condition
AI02029D
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Status Register Figure 7 shows the position of the Status Register in the control logic of the device. This register contains a number of control bits and status bits, as shown in Table 2. Bits b7, b6, b5 and b4 are always read as 1. WIP bit. The Write In Progress bit is a volatile read-only bit that is automatically set and reset by the internal logic of the device. When set to a 1, it indicates that the memory is busy with a Write cycle. WEL bit. The Write Enable Latch bit is a volatile read-only bit that is set and reset by specific instructions. When reset to 0, no WRITE or WRSR instructions are accepted by the device. BP1, BP0 bits. The Block Protect bits are nonvolatile read-write bits. These bits define the area of memory that is protected against the execution of Write cycles, as summarized in Table 3.
Table 2. Status Register Format
b7 1 1 1 1 BP1 BP0 WEL b0 WIP
Block Protect Bits Write Enable Latch Bit Write In Progress Bit
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Data Protection and Protocol Control To help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. The main security measures can be summarized as follows: - The WEL bit is reset at power-up. - Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to start a nonvolatile Write cycle (in the memory array or in the Status Register). - Accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. - Invalid Chip Select (S) and Hold (HOLD) transitions are ignored.
For any instruction to be accepted and executed, Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the next rising edge of Serial Clock (C). For this, "the last bit of the instruction" can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except in the case of RDSR and READ instructions). Moreover, the "next rising edge of CLOCK" might (or might not) be the next bus transaction for some other device on the bus. When a Write cycle is in progress, the device protects it against external interruption by ignoring any subsequent READ, WRITE or WRSR instruction until the present cycle is complete.
Table 3. Write-Protected Block Size
Status Register Bits Protected Block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory M95040 none 180h - 1FFh 100h - 1FFh 000h - 1FFh M95020 none C0h - FFh 80h - FFh 00h - FFh M95010 none 060h - 7Fh 040h - 7Fh 000h - 7Fh Array Addresses Protected
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MEMORY ORGANIZATION The memory is organized as shown in Figure 7. Figure 7. Block Diagram
HOLD W S C D Q Control Logic
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register
Size of the Read only EEPROM area
Y Decoder
1 Page
X Decoder
AI01272C
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INSTRUCTIONS Each instruction starts with a single-byte code, as summarized in Table 4. If an invalid instruction is sent (one not contained in Table 4), the device automatically deselects itself.
Table 4. Instruction Set
Instruc tion WREN WRDI RDSR WRSR READ WRITE Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 A8011 0000 A8010
Note: 1. A8 = 1 for the upper half of the memory array of the M95040, and 0 for the lower half, and is Don't Care for other devices. 2. X = Don't Care.
Figure 8. Write Enable (WREN) Sequence
S 0 C Instruction D High Impedance Q
AI01441D
1
2
3
4
5
6
7
Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High.
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Figure 9. Write Disable (WRDI) Sequence
S 0 C Instruction D High Impedance Q
AI03790D
1
2
3
4
5
6
7
Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: - Power-up - WRDI instruction execution - WRSR instruction completion - WRITE instruction completion - Write Protect (W) line being held Low.
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Figure 10. Read Status Register (RDSR) Sequence
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB
AI01444D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 6 5 4 3 2 1 0 7
Read Status Register (RDSR) One of the major uses of this instruction is to allow the MCU to poll the state of the Write In Progress (WIP) bit. This is needed because the device will not accept further WRITE or WRSR instructions when the previous Write cycle is not yet finished. As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current state of the bits in the Status Register is shifted out, on Serial Data Out (Q). The Read Cycle is terminated by driving Chip Select (S) High. The Status Register may be read at any time, even during a Write cycle (whether it be to the memory area or to the Status Register). All bits of the Status Register remain valid, and can be read using the RDSR instruction. However, during the current Write cycle, the values of the non-volatile bits (BP0, BP1) become frozen at a constant value. The updated value of these bits becomes available when a new RDSR instruction is executed, after completion of the Write cycle. On the other hand, the two read-only bits (Write Enable Latch (WEL), Write In Progress (WIP)) are dynamically updated during the on-going Write cycle.
The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted. BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
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Figure 11. Write Status Register (WRSR) Sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI01445B
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
Write Status Register (WRSR) This instruction has no effect on bits b7, b6, b5, b4, b1 and b0 of the Status Register. As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and data byte are then shifted in on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High. Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches the eighth bit of the data byte, and before the the next rising edge of Serial Clock (C). If this condition is not met, the Write Status Register (WRSR) instruction is not executed. The self-
timed Write Cycle starts, and continues for a period tW (as specified in Tables 17 to 20), at the end of which the Write in Progress (WIP) bit is reset to 0. The instruction is not accepted, and is not executed, under the following conditions: - if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) - if a Write Cycle is already in progress - if the device has not been deselected, by Chip Select (S) being driven High, after the eighth bit, b0, of the data byte has been latched in - if Write Protect (W) is Low.
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Figure 12. Read from Memory Array (READ) Sequence
S 0 C Instruction Byte Address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 Data Out 7 6 5 4 3 2 1 0
AI01440E
High Impedance Q
Note: Depending on the memory size, as shown in Table 5, the most significant address bits are Don't Care.
Read from Memory Array (READ) As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and address byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in Table 4. The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven Low, an internal bit-pointer is automatically incremented at each clock cycle, and the corresponding data bit is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Table 5. Address Range Bits
Device Address Bits M95040 A8-A0 M95020 A7-A0 M95010 A6-A0
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Figure 13. Byte Write (WRITE) Sequence
S 0 C Instruction Byte Address Data Byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
High Impedance Q
AI01442D
Note: Depending on the memory size, as shown in Table 5, the most significant address bits are Don't Care.
Write to Memory Array (WRITE) As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High after the rising edge of Serial Clock (C) that latches the last data bit, and before the next rising edge of Serial Clock (C) occurs anywhere on the bus. In the case of Figure 13, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in Tables 17 to 20), at the end of which the Write in Progress (WIP) bit is reset to 0. If, though, Chip Select (S) continues to be driven Low, as shown in Figure 14, the next byte of input data is shifted in. In this way, all the bytes from the
given address to the end of the same page can be programmed in a single instruction. If Chip Select (S) still continues to be driven Low, the next byte of input data is shifted in, and is used to overwrite the byte at the start of the current page. The instruction is not accepted, and is not executed, under the following conditions: - if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) - if a Write cycle is already in progress - if the device has not been deselected, by Chip Select (S) being driven High, at a byte boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and before the next rising edge of Serial Clock (C) occurs anywhere on the bus) - if Write Protect (W) is Low or if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
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Figure 14. Page Write (WRITE) Sequence
S 0 C Instruction Byte Address Data Byte 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
7
S 10+8N 11+8N 12+8N 13+8N 14+8N 15+8N 8+8N 9+8N
136
137
138
139
140
141 2
142 1
24 25 26 27 28 29 30 31 C Data Byte 2
Data Byte N
Data Byte 16
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
0
AI01443D
Note: Depending on the memory size, as shown in Table 5, the most significant address bits are Don't Care.
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POWER-UP AND DELIVERY STATE Power-up State After Power-up, the device is in the following state: - low power Stand-by mode - deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). - not in the Hold Condition - the Write Enable Latch (WEL) is reset to 0 - Write In Progress (WIP) is reset to 0 the BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). Initial Delivery State The device is delivered with the memory array set at all 1s (FFh). The Block Protect (BP1 and BP0) bits are initialized to 0.
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 6. Absolute Maximum Ratings
Symbol TSTG TLEAD VO VI VCC VESD Storage Temperature Lead Temperature during Soldering Output Voltage Input Voltage Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 PDIP: 10 seconds SO: 20 seconds (max) 1 TSSOP: 20 seconds (max) 1 -0.3 -0.3 -0.3 -4000 Parameter Min. -65 Max. 150 260 235 235 VCC+0.6 6.5 6.5 4000 Unit C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 7. Operating Conditions (M950x0)
Symbol VCC TA Ambient Operating Temperature (range 3) -40 125 C Supply Voltage Ambient Operating Temperature (range 6) Parameter Min. 4.5 -40 Max. 5.5 85 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 8. Operating Conditions (M950x0-W)
Symbol VCC TA Ambient Operating Temperature (range 3) -40 125 C Supply Voltage Ambient Operating Temperature (range 6) Parameter Min. 2.5 -40 Max. 5.5 85 Unit V C
Table 9. Operating Conditions (M950x0-S)
Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 1.8 -20 Max. 3.6 85 Unit V C
Table 10. AC Measurement Conditions
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Parameter
Min. 100
Max.
Unit pF
50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
ns V V
Figure 15. AC Measurement I/O Waveform
Input Levels 0.8VCC
Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
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Table 11. Capacitance
Symbol COUT CIN Parameter Output Capacitance (Q) Input Capacitance (D) Input Capacitance (other pins) Test Condition VOUT = 0V VIN = 0V VIN = 0V Min. Max. 8 8 6 Unit pF pF pF
Note: Sampled only, not 100% tested, at TA=25C and a frequency of 5 MHz.
Table 12. DC Characteristics (M950x0, temperature range 6)
Symbol ILI ILO ICC ICC1 VIL VIH VOL1 VOH1 Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1 VCC/0.9. VCC at 5 MHz, VCC = 5 V, Q = open S = VCC, VIN = VSS or VCC , VCC = 5 V - 0.3 0.7 VCC Min. Max. 2 2 5 10 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 13. DC Characteristics (M950x0, temperature range 3)
Symbol ILI ILO ICC ICC1 VIL VIH VOL1 VOH1 Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1 VCC/0.9. VCC at 5 MHz, VCC = 5 V, Q = open S = VCC, VIN = VSS or VCC , VCC = 5 V - 0.3 0.7 VCC Min. Max. 2 2 5 10 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
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Table 14. DC Characteristics (M950x0-W, temperature range 6)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.5 mA, VCC = 2.5 V IOH = -0.4 mA, VCC = 2.5 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1 VCC/0.9. VCC at 2 MHz, VCC = 2.5 V, Q = open S = VCC, VIN = VSS or VCC , VCC = 2.5 V - 0.3 0.7 VCC Min. Max. 2 2 2 2 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V
Table 15. DC Characteristics (M950x0-W, temperature range 3)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.5 mA, VCC = 2.5 V IOH = -0.4 mA, VCC = 2.5 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1 VCC/0.9. VCC at 2 MHz, VCC = 2.5 V, Q = open S = VCC, VIN = VSS or VCC , VCC = 2.5 V - 0.3 0.7 VCC Min. Max. 2 2 2 5 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V
Table 16. DC Characteristics (M950x0-S)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 0.15 mA, VCC = 1.8 V IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1 VCC/0.9. VCC at 1 MHz, VCC = 1.8 V, Q = open S = VCC, VIN = VSS or VCC , VCC = 1.8 V - 0.3 0.7 VCC Min.1 Max.1 2 2 2 2 0.3 VCC VCC+1 0.3 Unit A A mA A V V V V
Note: 1. Preliminary data, for the 1.8V to 3.6 supply voltage range devices.
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M95040, M95020, M95010
Table 17. AC Characteristics (M950x0, temperature range 6)
Test conditions specified in Table 10 and Table 7 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 50 50 50 100 10 20 30 70 40 60 60 100 60 Parameter Min. D.C. 90 90 100 90 90 90 90 1 1 Max. 5 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production.
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Table 18. AC Characteristics (M950x0, temperature range 3)
Test conditions specified in Table 10 and Table 7 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 100 100 100 150 10 40 50 100 90 120 120 150 150 Parameter Min. D.C. 100 100 200 100 200 200 200 1 1 Max. 2 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production.
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Table 19. AC Characteristics (M950x0-W, temperature ranges 6 and 3)
Test conditions specified in Table 10 and Table 8 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 100 100 100 250 10 40 50 140 90 120 120 250 150 Parameter Min. D.C. 200 200 200 200 200 200 200 1 1 Max. 2 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production.
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M95040, M95020, M95010
Table 20. AC Characteristics (M950x0-S)
Test conditions specified in Table 10 and Table 9 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 200 200 250 500 10 60 100 350 200 250 250 500 380 Parameter Min. D.C. 400 400 300 400 400 400 400 1 1 Max. 1 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production.
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M95040, M95020, M95010
Figure 16. Serial Input Timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
Figure 17. Hold Timing
S tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI02032
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M95040, M95020, M95010
Figure 18. Output Timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449D
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M95040, M95020, M95010
PACKAGE MECHANICAL PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
b2 A2 A1 b e A L
E
c eA eB
D
8
E1
1 PDIP-B
Notes: 1. Drawing is not to scale.
PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm Symb. Typ. A A1 A2 b b2 c D E E1 e eA eB L 3.30 2.92 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 - - 4.95 0.56 1.78 0.36 10.16 8.26 7.11 - - 10.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 Min. Max. 5.33 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 - - 0.195 0.022 0.070 0.014 0.400 0.325 0.280 - - 0.430 0.150 Typ. Min. Max. 0.210 inches
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M95040, M95020, M95010
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: Drawing is not to scale.
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
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M95040, M95020, M95010
TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
Notes: 1. Drawing is not to scale.
TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm Symbol Typ. A A1 A2 b c CP D e E E1 L L1 3.000 0.650 6.400 4.400 0.600 1.000 0 8 2.900 - 6.200 4.300 0.450 1.000 0.050 0.800 0.190 0.090 Min. Max. 1.200 0.150 1.050 0.300 0.200 0.100 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295 inches
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M95040, M95020, M95010
PART NUMBERING Table 21. Ordering Information Scheme
Example: Device Type M95 = SPI serial access EEPROM Device Function3 040 = 4 Kbit (512 x 8) 020 = 2 Kbit (256 x 8) 010 = 1 Kbit (128 x 8) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V S2 = VCC = 1.8 to 3.6V Package BN = PDIP8 MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) Temperature Range 6 = -40 to 85 C 31 = -40 to 125 C 5 = -20 to 85 C Option TR = Tape & Reel Packing
Note: 1. Temperature range available only on request. 2. The -S version (VCC range 1.8 V to 3.6 V) only available in temperature range 5. 3. All devices use a positive clock strobe: Serial Data In (D) is strobed on the rising edge of Serial Clock (C) and Serial Data Out (Q) is synchronized from the falling edge of Serial Clock (C).
M95040
-
W MN
6
TR
For a list of available options (speed, package, etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
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M95040, M95020, M95010
REVISION HISTORY Table 22. Document Revision History
Date 10-May-2000 16-Mar-2001 19-Jul-2001 11-Oct-2001 26-Feb-2002 27-Sep-2002 24-Oct-2002 24-Feb-2003 Rev. 2.2 2.3 2.4 3.0 3.1 3.2 3.3 3.4 Description of Revision s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte Write Operation Human Body Model meets JEDEC std (Table 2). Minor adjustments to Figs 7,9,10,11 & Tab 9. Wording changes, according to the standard glossary Illustrations and Package Mechanical data updated Temperature range `3' added to the -W supply voltage range in DC and AC characteristics Document reformatted using the new template Description of chip deselect after 8th clock pulse made more explicit Position of A8 in Read Instruction Sequence Figure corrected. Load Capacitance CL changed Minimum values for tCHHL and tCHHH changed. Description of Read from Memory Array (READ) instruction corrected, and clarified
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M95040, M95020, M95010
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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